HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 46

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 11.2
Section 12 Timer Unit (TMU)
Table 12.1
Table 12.2
Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1
Table 14.2
Table 14.3
Table 14.4
Table 14.4
Table 14.4
Table 14.4
Table 14.5
Table 14.6
Section 15 Realtime Clock (RTC)
Table 15.1
Table 15.2
Section 16 Serial Communication Interface with FIFO (SCIF)
Table 16.1
Table 16.2
Table 16.3
Table 16.4
Section 17 Infrared Data Association Module (IrDA)
Table 17.1
Section 18 USB Function Module
Table 18.1
Table 18.2
Section 19 Pin Function Controller
Table 19.1
Section 20 I/O Ports
Table 20.1
Table 20.2
Table 20.3
Table 20.4
Table 20.5
Table 20.6
Table 20.7
Table 20.8
Table 20.9
Rev. 2.00, 09/03, page xliv of xlvi
Pin Configuration ............................................................................................. 295
Pin Configuration ............................................................................................. 311
TMU Interrupt Sources..................................................................................... 322
TPU Functions ................................................................................................. 330
Pin Configuration ............................................................................................. 332
TPU Clock Sources .......................................................................................... 335
TPSC2 to TPSC0 (1) ........................................................................................ 335
TPSC2 to TPSC0 (2) ........................................................................................ 335
TPSC2 to TPSC0 (3) ........................................................................................ 336
TPSC2 to TPSC0 (4) ........................................................................................ 336
IOA2 to IOA0 .................................................................................................. 338
Register Combinations in Buffer Operation....................................................... 346
Pin Configuration ............................................................................................. 353
Recommended Oscillator Circuit Constants (Recommended Values)................. 372
Pin Configuration ............................................................................................. 378
SCSMR Settings for Serial Transfer Format Selection....................................... 403
Serial Transfer Formats .................................................................................... 404
SCIF Interrupt Sources ..................................................................................... 427
Pin Configuration ............................................................................................. 432
Pin Configuration ............................................................................................. 439
Command Decoding on Application Side.......................................................... 464
Multiplex Pins.................................................................................................. 475
Port A Data Register (PADR) Read/Write Operations ....................................... 508
Port B Data Register (PBDR) Read/Write Operations ....................................... 509
Port C Data Register (PCDR) Read/Write Operations ....................................... 511
Port D Data Register (PDDR) Read/Write Operations ....................................... 512
Port E Data Register (PEDR) Read/Write Operations........................................ 514
Port F Data Register (PFDR) Read/Write Operations ........................................ 515
Port G Data Register (PGDR) Read/Write Operations ....................................... 516
Port H Data Register (PHDR) Read/Write Operations ....................................... 517
Port J Data Register (PJDR) Read/Write Operations.......................................... 519