HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 202

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3.2
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The correspondence
between the external pins (MD3, MD4) and memory size is listed in the table below.
Table 7.3
MD4
0
1
For areas other than area 0, byte, word, and longword may be chosen for the bus width using
CSnBCR that can be set in each area. The bus width that can be set differs according to a
connected interface. For more details, see the CSn Bus Control Register.
Rev. 2.00, 09/03, page 154 of 690
H'C0000000
H'A0000000
H'E0000000
Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can
H'00000000
H'20000000
H'40000000
H'60000000
H'80000000
optionally generate a physical address for the logical address. This figure can be applied when
MMU is off and when the MMU is on and each physical address for the logical address is equal
except for higher three bits. When translating a logical address to a physical address, refer to
table 7.2.
Memory Bus Width
Correspondence between External Pins (MD3 and MD4) and Memory Size
Logical address space
MD3
0
1
0
1
P0
P1
P2
P3
P4
Figure 7.2 Address Space
Memory Size
Setting prohibited
8 bits
16 bits
32 bits
Physical address space
Reserved area
Area 5A (CS5A)
Area 5B (CS5B)
Area 6A (CS6A)
Area 6B (CS6B)
Area 0 (CS0)
Area 2 (CS2)
Area 3 (CS3)
Area 4 (CS4)
Internal I/O
H'00000000
H'04000000
H'08000000
H'0C000000
H'10000000
H'14000000
H'16000000
H'18000000
H'1A000000
H'1BFFFFFF