HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 485

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI incorporates a USB function module (USB).
18.1
Endpoint
Name
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
IFUSB40A_000020020100
The UDC (USB device controller) conforming to USB2.0 and transceiver process USB
protocol automatically.
Automatic processing of USB standard commands for endpoint 0 (some commands and
class/vendor commands require decoding and processing by firmware)
Transfer speed: Full-speed
Endpoint configuration:
Interrupt requests: Generates various interrupt signals necessary for USB
transmission/reception
Clock: External input (48 MHz) (Refer to section 9.4.1, Frequency Control Register (FRQCR),
and section 9.4.2, USB Clock Frequency Control Register (UCLKCR))
Power-down mode
Power consumption can be reduced by stopping UDC internal clock when USB cable is
disconnected
Automatic transition to/recovery from suspend state
Can be connected to a Philips PDIUSBP11 Series transceiver or compatible product in internal
transceiver bypass mode (the XVEROFF bit in XVERCR is set to 1)
When using a compatible product, carry out evaluation and investigation with the
manufacturer supplying the transceiver beforehand.
Power mode: Self-powered
Features
Configuration 1
Abbreviation Transfer Type
EP0s
EP0i
EP0o
EP1
EP2
EP3
Section 18 USB Function Module
Setup
Control-in
Control-out
Bulk-out
Bulk-in
Interrupt
Interface 0
Maximum
Packet Size
8
8
8
64
64
8
Alternate Setting 0
FIFO Buffer
Capacity (Byte)
8
8
8
128
128
8
Rev. 2.00, 09/03, page 437 of 690
Endpoint 1
Endpoint 2
Endpoint 3
DMA Transfer
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Possible
Possible
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