HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 303

MPU 3V 0K PB-FREE 208 FP

HD6417705F133BV

Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417705F133BV

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Table 8.4
DL
0
1
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used for level detection, there are the following two cases depending on the timing
to detect the next DREQ after outputting DACK. A case wherein transfer is aborted after the same
number of transfers has been performed as requests (overrun 0) and wherein another transfer is
aborted after transfers have been performed for (the number of requests plus 1) times (overrun 1).
The DO bit in CHCR selects overrun 0 or overrun 1.
Table 8.5
CHCR_0 or CHCR_1
DO
0
1
CHCR_0 or CHCR_1
Selecting External Request Detection with DL, DS Bits
Selecting External Request Detection with DO Bit
DS
0
1
0
1
External Request
Overrun 0
Overrun 1
Detection of External Request
Low level detection
Falling edge detection
High level detection
Rising edge detection
Rev. 2.00, 09/03, page 255 of 690

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