HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 32

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.4 Operation .................................................................................................................... 533
21.5 Interrupts and DMAC Transfer Request ....................................................................... 536
21.6 Definitions of A/D Conversion Accuracy ..................................................................... 536
21.7 Usage Notes................................................................................................................. 538
Section 22 User Break Controller ...................................................................541
22.1 Features....................................................................................................................... 541
22.2 Register Descriptions................................................................................................... 543
22.3 Operation .................................................................................................................... 555
Section 23 User Debugging Interface (UDI)...................................................567
23.1 Features....................................................................................................................... 567
Rev. 2.00, 09/03, page xxx of xlvi
21.4.1 Single Mode.................................................................................................... 533
21.4.2 Multi Mode ..................................................................................................... 533
21.4.3 Scan Mode ...................................................................................................... 534
21.4.4 Input Sampling and A/D Conversion Time....................................................... 534
21.7.1 Allowable Signal-Source Impedance................................................................ 538
21.7.2 Influence to Absolute Accuracy....................................................................... 538
21.7.3 Setting Analog Input Voltage........................................................................... 538
21.7.4 Notes on Board Design.................................................................................... 539
21.7.5 Notes on Countermeasures to Noise................................................................. 539
22.2.1 Break Address Register A (BARA).................................................................. 543
22.2.2 Break Address Mask Register A (BAMRA) ..................................................... 544
22.2.3 Break Bus Cycle Register A (BBRA)............................................................... 544
22.2.4 Break Address Register B (BARB) .................................................................. 545
22.2.5 Break Address Mask Register B (BAMRB) ..................................................... 546
22.2.6 Break Data Register B (BDRB) ....................................................................... 546
22.2.7 Break Data Mask Register B (BDMRB)........................................................... 547
22.2.8 Break Bus Cycle Register B (BBRB) ............................................................... 547
22.2.9 Break Control Register (BRCR)....................................................................... 549
22.2.10 Execution Times Break Register (BETR)......................................................... 552
22.2.11 Branch Source Register (BRSR) ...................................................................... 553
22.2.12 Branch Destination Register (BRDR)............................................................... 554
22.2.13 Break ASID Register A (BASRA) ................................................................... 554
22.2.14 Break ASID Register B (BASRB).................................................................... 555
22.3.1 Flow of the User Break Operation.................................................................... 555
22.3.2 Break on Instruction Fetch Cycle ..................................................................... 557
22.3.3 Break on Data Access Cycle ............................................................................ 558
22.3.4 Sequential Break ............................................................................................. 559
22.3.5 Value of Saved Program Counter..................................................................... 559
22.3.6 PC Trace ......................................................................................................... 561
22.3.7 Usage Examples.............................................................................................. 562
22.3.8 Notes............................................................................................................... 566