HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 44

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 1 Overview
Table 1.1
Table 1.2
Table 1.3
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Section 3 Memory Management Unit (MMU)
Table 3.1
Section 4 Cache
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Table 4.6
Table 4.7
Table 4.8
Section 5 Exception Handling
Table 5.1
Section 6 Interrupt Controller (INTC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Rev. 2.00, 09/03, page xlii of xlvi
SH7705 Features...................................................................................................... 2
Pin Functions ........................................................................................................... 9
Pin Functions ......................................................................................................... 17
Logical Address Space ........................................................................................... 28
Register Initial Values ............................................................................................ 30
Addressing Modes and Effective Addresses for CPU Instructions ........................... 42
CPU Instruction Formats........................................................................................ 45
CPU Instruction Types ........................................................................................... 48
Data Transfer Instructions ...................................................................................... 52
Arithmetic Operation Instructions........................................................................... 54
Logic Operation Instructions .................................................................................. 56
Shift Instructions.................................................................................................... 57
Access States Designated by D, C, and PR Bits....................................................... 80
Number of Entries and Size/Way in Each Cache Size ............................................. 93
LRU and Way Replacement (when Cache Locking Mechanism Is Disabled)........... 95
Way Replacement when a PREF Instruction Misses the Cache................................ 99
Way Replacement when Instructions other than
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 0).................... 99
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK = 1).................... 99
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK = 1).................. 100
Address Format Based on Size of Cache to be Assigned to Memory...................... 106
Exception Event Vectors ...................................................................................... 116
Pin Configuration................................................................................................. 127
Interrupt Sources and IPRA to IPRH..................................................................... 128
I R L 3
Interrupt Exception Handling Sources and Priority (IRQ Mode)............................ 140
the PREF Instruction Miss the Cache...................................................................... 99
Branch Instructions ............................................................................................ 58
System Control Instructions................................................................................ 59
Operation Code Map .......................................................................................... 62
to
I R L 0
Pins and Interrupt Levels ................................................................ 138
Tables