HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 598

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 2.00, 09/03, page 550 of 690
Bit
15
14
13
12
11
10
Bit
Name
SCMFCA
SCMFCB
SCMFDA
SCMFDB
PCTE
PCBA
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions set
for channel A is satisfied, this flag is set to 1. In order to
clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not match
1: The L bus cycle condition for channel A matches
L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions set
for channel B is satisfied, this flag is set to 1. In order to
clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not match
1: The L bus cycle condition for channel B matches
I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions set for
channel A is satisfied, this flag is set to 1. In order to clear
this flag, write 0 into this bit.
0: The I bus cycle condition for channel A does not match
1: The I bus cycle condition for channel A matches
I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions set for
channel B is satisfied, this flag is set to 1. In order to clear
this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not match
1: The I bus cycle condition for channel B matches
PC Trace Enable
0: Disables PC trace
1: Enables PC trace
PC Break Select A
Selects the break timing of the instruction fetch cycle for
channel A as before or after instruction execution.
0: PC break of channel A is set before instruction execution
1: PC break of channel A is set after instruction execution