HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 50

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 1.1
Rev. 2.00, 09/03, page 2 of 690
Item
CPU
Memory
management
unit (MMU)
Cache memory
Interrupt
controller (INTC)
SH7705 Features
Features
Original Renesas SuperH architecture
Compatible with SH-1, SH-2 and SH-3 at object code level
32-bit internal data bus
General-registers
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Five 32-bit control registers
Four 32-bit system registers
RISC-type instruction set
Instruction length: 16-bit fixed length and improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
Instruction execution time: one instruction/cycle for basic instructions
Logical address space: 4 Gbytes
Five-stage pipeline
4 Gbytes of address space, 256 address space identifiers (ASID: 8 bits)
Page unit sharing
Supports multiple page sizes: 1 kbyte or 4 kbytes
128-entry, 4-way set associative TLB
Supports software selection of replacement method and random-
replacement algorithms
Contents of TLB are directly accessible by address mapping
32-kbyte cache, mixture of instructions and data
512 entries, 4-way set associative, 16-byte block length
Write-back, write-through, LRU replacement algorithm
1-stage write-back buffer
Seven external interrupt pins (NMI, IRQ5 to IRQ0)
On-chip peripheral interrupt: Priority level is independently selected for each
module