HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 209

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. When the CS5B space is specified as address/data multiplex I/O (MPX), specify the
When the memory type is specified to an area other than the areas that can be specified, the
operation of this LSI is not guaranteed.
7.4.3
CSnWCR is a 32-bit readable/writable register that specifies various wait cycles for memory
accesses. The bit configuration of this register varies as shown below according to the memory
type (TYPE 2, TYPE 1, or TYPE 0) specified by the CSn space bus control register (CSnBCR).
Specify the CSnWCR register before accessing the target area. Specify CSnBCR register first,
then specify the CSnWCR register.
Bit
8 to 0
2. The data bus size of the CS0 space is specified by an external input pin. The value of
3. When both the CS2 and CS3 spaces are specified as the SDRAM space, specify the
4. When the CS2 or CS3 space is specified as the SDRAM space, specify the bus width to
5. The SDRAM bank active mode can only be used for the CS3 space. (Refer to the
6. The initial values of the bus size assignment for areas 5B, 6A, and 6B after power-on
7. When port A or B is used, specify the bus size of all areas to 8 bits or 16 bits.
Bit
Name
CSn Space Wait Control Register (CSnWCR) (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
bus size to 16 bits.
BSZ[1:0] bits in CS0BCR are invalid.
same bus size for the CS2 and CS3 spaces.
16 bits or 32 bits.
explanation of the BACTV bit in the SDRAM control register.)
reset is specified to prohibited setting. Therefore, specify the 8- or 16-bit size before
accessing these areas.
Initial
Value
0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/03, page 161 of 690