HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 185

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.3
IRL interrupts are input by level at pins
indicated by pins
interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request
(interrupt priority level 0). Figure 6.2 shows an examples of an IRL interrupt connection. Table
6.3 shows
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every peripheral clock remain unchanged for two consecutive cycles, so that no
transient level on the
stopped, noise cancellation is performed using the clock for the RTC instead. Therefore when the
RTC is not used, recovery from standby mode by means of IRL interrupts cannot be performed in
standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt processing starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by
processing.
IRL Interrupts
I R L
Interrupt
request
pin and interrupt levels.
I R L 3
I R L
Figure 6.2 Example of IRL Interrupt Connection
to
I R L 0
pin change is detected. In standby mode, as the peripheral clock is
. An
I R L 3
encoder
I R L 3
Priority
to
I R L 0
to
I R L 0
IRL3 to IRL0
value of 0 (0000) indicates the highest-level
. The priority level is the higher of those
4
IRL3 to IRL0
Rev. 2.00, 09/03, page 137 of 690
This LSI
I R L
interrupt