HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 578

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

21.3.1
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion. Table 21.2 indicates the pairings of analog input channels and A/D data
registers that store the results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into bits 15 to 6 in the
A/D data register corresponding to the selected channel. Bits 5 to 0 of an A/D data register are
reserved bits that are always read as 0.
The A/D data registers are initialized to H'0000.
Table 21.2 Analog Input Channels and A/D Data Registers
21.3.2
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
Rev. 2.00, 09/03, page 530 of 690
Analog Input Channel
AN0
AN1
AN2
AN3
Bit
15
Bit
Name
ADF
A/D Data Registers A to D (ADDRA to ADDRD)
A/D Control/Status Registers (ADCSR)
Initial
Value
0
A/D Data Register that Store Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
R/W
R/(W) *
Description
A/D End Flag
Indicates the end of A/D conversion.
[Setting conditions]
Single mode: A/D conversion ends
Multi mode: A/D conversion ends cycling through the
selected channels
Scan mode: A/D conversion ends cycling through the
selected channels
[Clearing conditions]
(1) Reading ADF while ADF = 1, then writing 0 to ADF
(2) DMAC is activated by ADI interrupt and ADDR is
Note: * Clear this bit by writing 0. Writing 1 is ignored.
read