HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 73

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.1
Processing States and Processing Modes
2.1.1
Processing States
This LSI supports four types of processing states: a reset state, an exception handling state, a
program execution state, and a low-power consumption state, according to the CPU processing
states.
Reset State: In the reset state, the CPU is reset. The LSI supports two types of resets: power-on
reset and manual reset. For details on resets, refer to section 5, Exception Handling.
In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In
manual reset, the register contents of a part of the LSI on-chip modules, such as the bus state
controller (BSC), are retained. For details, refer to section 24, List of Registers. The CPU internal
statuses and registers are initialized both in power-on reset and manual reset. After initialization,
the program branches to address H'A0000000 to pass control to the reset processing program to be
executed.
Exception Handling State: In the exception handling state, the CPU processing flow is changed
temporarily by a general exception or interrupt exception processing. The program counter (PC)
and status register (SR) are saved in the save program counter (SPC) and save status register
(SSR), respectively. The program branches to an address obtained by adding a vector offset to the
vector base register (VBR) and passes control to the exception processing program defined by the
user to be executed. For details on reset, refer to section 5, Exception Handling.
Program Execution State: The CPU executes programs sequentially.
Low-Power Consumption State: The CPU stops operation to reduce power consumption. The
low-power consumption state can be entered by executing the SLEEP instruction. For details on
the low-power consumption state, refer to section 11, Power-Down Modes.
Figure 2.1 shows a status transition diagram.
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