HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 41

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 25.3 CKIO Clock Input Timing .................................................................................. 632
Figure 25.4 CKIO Clock Output Timing ................................................................................ 632
Figure 25.5 Power-On Oscillation Settling Time .................................................................... 633
Figure 25.6 Oscillation Settling Time at Standby Return (Return by Reset) ............................ 633
Figure 25.7 Oscillation Settling Time at Standby Return (Return by NMI) ............................. 633
Figure 25.8 Oscillation Settling Time at Standby Return
Figure 25.9 PLL Synchronization Settling Time by Reset or NMI .......................................... 634
Figure 25.10 PLL Synchronization Settling Time by IRQ/IRL, PINT Interrupts ..................... 635
Figure 25.11 PLL Synchronization Settling Time when Frequency Multiplication
Figure 25.12 Reset Input Timing ........................................................................................... 637
Figure 25.13 Interrupt Signal Input Timing ............................................................................ 637
Figure 25.14 Bus Release Timing .......................................................................................... 637
Figure 25.15 Pin Drive Timing at Standby ............................................................................. 638
Figure 25.16 Basic Bus Cycle (No Wait) ............................................................................... 640
Figure 25.17 Basic Bus Cycle (One Software Wait) ............................................................... 641
Figure 25.18 Basic Bus Cycle (One External Wait) ................................................................ 642
Figure 25.19 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM Bit = 0),
Figure 25.20 Address/Data Multiplex I/O Bus Cycle
Figure 25.21 Burst ROM Read Cycle
Figure 25.22 Synchronous DRAM Single Read Bus Cycle
Figure 25.23 Synchronous DRAM Single Read Bus Cycle
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read 4),
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read 4),
Figure 25.26 Synchronous DRAM Single Write Bus Cycle
Figure 25.27 Synchronous DRAM Single Write Bus Cycle
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write 4),
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write 4),
Figure 25.30 Synchronous DRAM Burst Read Bus Cycle (Single Read 4)
(Return by IRQ5 to IRQ0, PINT15 to PINT0, and
(Three Address Cycles, One Software Wait, One External Wait) ........................ 644
(One Access Wait, One External Wait, One Burst Wait, Two Bursts) ................. 645
(Auto Precharge, CAS Latency 2, TRCD 1 Cycle, TRP
(Auto Precharge, CAS Latency 2, TRCD 2 Cycle, TRP
(Auto Precharge, CAS Latency 2, TRCD 1 Cycle, TRP
(Auto Precharge, CAS Latency 2, TRCD 2 Cycle, TRP
(Auto Precharge, TRWL = 2 Cycle) ................................................................... 650
(Auto Precharge, TRCD 3 Cycle, TRWL = 2 Cycle) ....................................... 651
(Auto Precharge, TRCD 1 Cycle, TRWL = 2 Cycle) ....................................... 652
(Auto Precharge, TRCD 2 Cycle, TRWL = 2 Cycle) ....................................... 653
(Bank Active Mode: ACTV + READ Commands, CAS Latency = 2,
TRCD = 1 Cycle).............................................................................................. 654
Ratio Modified ................................................................................................. 635
No Idle Cycle Setting) ...................................................................................... 643
I R L 3
Rev. 2.00, 09/03, page xxxix of xlvi
to
I R L 0
1 Cycle)............... 646
2 Cycle)............... 647
2 Cycle)............... 648
1 Cycle)............... 649
) ......................... 634