HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 218

• Manufacturer Part Number: HD6417705F133BV
• Description: MPU 3V 0K PB-FREE 208 FP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417705F133BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 105
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
6
5 to 0
CS4WCR
Bit
31 to 18
17
16
15 to 13
12
11
Rev. 2.00, 09/03, page 170 of 690
Bit
Name
WM
Bit
Name
BW1
BW0
SW1
SW0
Initial
Value
0
0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
Description
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address,
W E n
Specify the number of delay cycles from address and
assertion to
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Assertion
R D
and
W E n
assertion.
C S n
Assertion to
C S n
R D
,