HD6417705F133BV Renesas Electronics America, HD6417705F133BV Datasheet - Page 160

MPU 3V 0K PB-FREE 208 FP

HD6417705F133BV

Manufacturer Part Number
HD6417705F133BV
Description
MPU 3V 0K PB-FREE 208 FP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417705F133BV

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
105
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
5.1.4
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
5.1.5
TEA is assigned to address H'FFFFFFFC and stores the logical address for an exception
occurrence when an exception related to memory accesses occurs. TEA can be modified using the
software.
Rev. 2.00, 09/03, page 112 of 690
Bit
31 to 12
11 to 0
Bit
31 to 0
Interrupt Event Register 2 (INTEVT2)
Exception Address Register (TEA)
Bit Name
INTEVT2
Bit Name
TEA
Initial Value
0
Initial Value
R/W
R
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Description
Logical address for exception occurrence

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