HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 1033

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

32.3.8
Table 32.11 Peripheral Module Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module
RTC
SCI
Port
DMAC
Note: * P
cyc
Peripheral Module Signal Timing
Item
Oscillation settling time
Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time
(clock synchronization)
Receive data hold time
(clock synchronization)
RTS delay time
CTS setup time
(clock synchronization)
CTS hold time
(clock synchronization)
Output data delay time
Input data setup time (1)
Input data hold time (1)
Input data setup time (2)
Input data hold time (2)
Input data setup time (3)
Input data hold time (3)
DREQ setup time
DREQ hold time
DRAK delay time
stands for “peripheral clock (Pφ) cycle.”
Asynchronization
Clock synchronization
Symbol Min
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
ROSC
SCYC
SCKR
SCKF
SCKW
TXD
RXS
RXH
RTSD
CTSS
CTSH
PORTD
PORTS1
PORTH1
PORTS2
PORTH2
PORTS3
PORTH3
DRQS
DREQH
DRAKD
Rev.6.00 Mar. 27, 2009 Page 975 of 1036
—
4
6
—
—
0.4
—
100
100
—
100
100
—
15
8
t
8
3 t
8
8
8
—
cyc
cyc
Section 32 Electrical Characteristics
+ 15
+ 15 —
Max
3
—
—
1.5
1.5
0.6
100
—
—
100
—
—
26
—
—
—
—
—
—
—
14
REJ09B0254-0600
Unit
s
P
P
t
ns
ns
ns
Scyc
cyc
cyc
*
*
Figure
32.41
32.42
32.43
32.42
32.43
32.44
32.45
32.46