HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 289

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Break Condition Specified to a DMAC Data Access Cycle
1. Register specifications
8.3.9
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
on Y memory space. The X/Y-memory space is changed by a mode specification.
BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555,
BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F,
BRCR = H'00000080, BASRA = H'80, BASRB = H'70
Specified conditions: Channel A/channel B independent mode
•
•
On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles.
On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in
address H'00055555.
(1) A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
(2) Since the CPU has a pipeline configuration, the pipeline determines the order of an
(3) When the bus cycle condition for channel A is specified as a break before execution
Address:
Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition)
Address:
Data:
Bus cycle: DMAC/data access/write/byte
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
Channel A
Channel B
Usage Notes
H'00314156, Address mask: H'00000000, ASID: H'80
H'00055555, Address mask: H'00000000, ASID: H'70
H'00000078, Data mask: H'0000000F
Rev.6.00 Mar. 27, 2009 Page 231 of 1036
Section 8 User Break Controller
REJ09B0254-0600