HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 631

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 4: O/E
0
1
Bit 3—Stop Bit Length (STOP): Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of
the next incoming character.
Bit 3: STOP
0
1
Bit 2—Reserved: This bit is always read as 0. The write value should always be 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the internal clock
source of the on-chip baud rate generator. Four clock sources are available. Pφ, Pφ/4, Pφ/16 and
Pφ/64. For further information on the clock source, bit rate register 2 settings, and baud rate, see
section 19.2.8, Bit Rate Register 2 (SCBRR2).
Bit 1: CKS1
0
1
Note: Pφ: Peripheral clock
Description
Even parity.
If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an even number of 1s in the received character and
parity bit combined.
Odd parity.
If odd parity is selected, the parity bit is added to transmit data to make an odd
number of 1s in the transmitted character and parity bit combined. Receive data
is checked to see if it has an odd number of 1s in the received character and
parity bit combined.
Description
One stop bit.
In transmitting, a single bit of 1 is added at the end of each transmitted character.
Two stop bits.
In transmitting, two bits of 1 are added at the end of each transmitted character.
Bit 0: CKS0
0
1
0
1
Description
Pφ clock
Pφ/4 clock
Pφ/16 clock
Pφ/64 clock
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev.6.00 Mar. 27, 2009 Page 573 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)