HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 391

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX3 to AMX0 in MCR.
Table 12.12 shows the relationship between the address multiplex specification bits and the bits
output at the address pins. Table 12.13 shows the relationship between LSI address pins and
synchronous DRAM address pins.
A25 to A17 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs
longword address specification. Connection should therefore be made in the following order: with
a 32-bit bus width, connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect
pin A1 to pin A3; with a 16-bit bus width, connect pin A0 of the synchronous DRAM to pin A1 of
this LSI, then connect pin A1 and pin A2.
Figure 12.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
SH7727
CKIO, CKIO2
DQMLU
DQMLL
RD/WR
CKE
RAS
CAS
CSn
D15
A14
A13
A12
D0
A1
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Rev.6.00 Mar. 27, 2009 Page 333 of 1036
Section 12 Bus State Controller (BSC)
64M synchronous DRAM
(1M × 16-bit × 4-bank)
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A13
A12
A11
A0
CLK
CKE
CS
RAS
CAS
WE
DQ15
DQ0
DQMU
DQML
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REJ09B0254-0600