HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 584

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface (SCI)
Multiprocessor Serial Data Reception:
Figure 17.15 shows a sample flow chart for multiprocessor serial data reception. After enabling
the SCI reception, receive multiprocessor serial data following the procedure shown below:
Rev.6.00 Mar. 27, 2009 Page 526 of 1036
REJ09B0254-0600
No
No
No
Figure 17.15 Sample Multiprocessor Serial Reception Flowchart (1)
Read receive data in SCRDR
Read receive data in SCRDR
Set MPIE bit in SCSCR to 1
Clear RE bit in SCSCR to 0
Read RDRF bit in SCSSR
Read RDRF bit in SCSSR
FER = 1 or ORER = 1?
FER = 1 or ORER = 1?
Read ORER and FER
Read ORER and FER
All data received?
Start reception
bits in SCSSR
bits in SSCSR
End reception
station’s ID?
RDRF = 1?
RDRF = 1?
Yes
Is ID the
Yes
Yes
Yes
No
No
Yes
Yes
(4)
(1)
(2)
No
Error processing
(3)
(1) ID receive cycle:
(2) SCI status check and compare to
(3) SCI status check and data
(4) Receive error processing and break
Set the MPIE bit in the serial control
register (SCSCR) to 1.
ID reception:
Read the serial status register
(SCSSR), check that RDRF is set
to 1, then read data from the
receive data register (SCRDR) and
compare with the processor's own
ID. If the ID does not match the
receive data, set MPIE to 1 again
and clear RDRF to 0. If the ID
matches the receive data, clear
RDRF to 0.
receiving:
Read SCSSR, check that RDRF is
set to 1, then read data from the
receive data register (SCRDR).
detection:
If a receive error occurs, read the
ORER and FER bits in SCSSR to
identify the error. After executing
the necessary error processing,
clear both ORER and FER to 0.
Receiving cannot resume if ORER
or FER remain set to 1. When a
framing error occurs, the RxD0 pin
can be read to detect the break
state.