HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 588

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 Serial Communication Interface (SCI)
Communication Format
The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added.
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control
register (SCSCR). See table 17.10.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK0 pin. Eight
clock pulses are output per transmitted or received character. When the SCI is not transmitting or
receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2-
character units, so a 16 pulse synchronization clock is output. To receive in 1-character units,
select an external clock source.
Transmitting and Receiving Data
SCI Initialization (clock synchronous mode)
Before transmitting and receiving data, the TE and RE bits in SCSCR should be cleared to 0, then
the SCI should be initialized as described in a sample flowchart in figure 17.18.
When the operating mode, or transfer format, is changed for example, the TE and RE bits must be
cleared to 0 before making the change using the following procedure. When the TE bit is cleared
to 0, the TDRE flag is set to 1 and the transmit shift register (SCTSR) is initialized.
Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and
ORER flags, or the contents of SCRDR.
Figure 17.18 is a sample flowchart for initializing the SCI.
Rev.6.00 Mar. 27, 2009 Page 530 of 1036
REJ09B0254-0600