HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 12

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Rev.6.00 Mar. 27, 2009 Page x of lvi
REJ09B0254-0600
Page
543
601
634
635
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18.1 Overview
As an additional serial communications
interface function (SCI), an IC card (smart
card) interface that is compatible to the
ISO/IEC standard 7816-3 for identification
of cards is supported. ...
Section 19 Serial Communication Interface
with FIFO (SCIF)
TxD/TXD, RxD/RXD, CTS, RTS
19.5 Usage Notes
4. Sending a Break Signal: The I/O
condition and level of the TxD pin are
determined SCP4DT bit in the port SC data
register 2 (SCPDR2) and bits SCP4MD0
and SCP4MD1 port SC control register 2
(SCPCR2). This feature can be used to
send a break signal. To send a break signal
during serial transmission, clear the CP4DT
bit to 0 (designating level), then set the
SCP4MD0 and SCP4MD1 bits to 0 and 1,
respectively, and finally clear the TE bit to 0
(halting transmission). When the TE bit is
cleared to 0, the transmitter is initialized
regardless of the current transmission
state, and 0 is output from the TxD pin.
Section 20 Serial IO (SIOF)
SIOFSYN, SIORXD
20.3.4 Register Assignment for Transfer
Data
Note: In figure 20.5, only data portions that
are shown by the oblique lines are
transmitted or received as effective data.
Thus, it is necessary to transmit in byte for
8 bit data and in word 16 bit data. The
areas without the oblique lines are not the
object to transmit or receive.
Table 20.6 Transmit Data Sound Mode
Mode
Monaural
Stereo
Same sound for right and left
Previous Version
TDLE
1
1
1
TDRE
0
1
1
Bit
TDREP
*
0
1
As an additional serial communications
interface function, a smart card (integrated
circuit card) interface (SCI) that is
compatible with the T = 0 data transfer
protocol of ISO/IEC standard 7816-3
(identification card) is supported. ...
TxD2, RxD2, CTS2, RTS2
4. Sending a Break Signal: The I/O
condition and level of the TxD pin are
determined SCP4DT bit in the port SC data
register 2 (SCPDR2) and bits SCP4MD0
and SCP4MD1 port SC control register 2
(SCPCR2). This feature can be used to
send a break signal. To send a break signal
during serial transmission, clear the CP4DT
bit to 0 (designating level), then set the
SCP4MD0 and SCP4MD1 bits to 1 and 0,
respectively, and finally clear the TE bit to 0
(halting transmission). When the TE bit is
cleared to 0, the transmitter is initialized
regardless of the current transmission
state, and 0 is output from the TxD pin.
SIOFSYNC, RxD_SIO
Note: In figure 20.5, only data portions that
are shown by the oblique lines are
transmitted or received as effective data.
Thus, the areas without the oblique lines
are not the object to transmit or receive.
Mode
Monaural
Stereo
Same sound for right and left
Revised Version
TDLE
1
1
1
TDRE
0
1
1
Bit
TLREP
*
0
1