HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 22

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.3
7.4
7.5
Section 8 User Break Controller
8.1
8.2
Rev.6.00 Mar. 27, 2009 Page xx of lvi
REJ09B0254-0600
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
INTC Registers ................................................................................................................. 179
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Interrupt Request Register 3 (IRR3) .................................................................... 192
7.3.11 Interrupt Request Register 4 (IRR4) .................................................................... 195
INTC Operation ................................................................................................................ 197
7.4.1
7.4.2
Interrupt Response Time ................................................................................................... 199
Overview........................................................................................................................... 203
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 206
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Execution Times Break Register (BETR)............................................................ 218
8.2.11 Branch Source Register (BRSR).......................................................................... 219
8.2.12 Branch Destination Register (BRDR).................................................................. 220
8.2.13 Break ASID Register A (BASRA)....................................................................... 221
IRQ Interrupt........................................................................................................ 169
IRL Interrupts ...................................................................................................... 170
PINT Interrupt...................................................................................................... 172
On-Chip Supporting Module Interrupts ............................................................... 172
Interrupt Exception Handling and Priority........................................................... 173
Interrupt Priority Registers A to G (IPRA to IPRG) ............................................ 179
Interrupt Control Register 0 (ICR0)..................................................................... 180
Interrupt Control Register 1 (ICR1)..................................................................... 181
Interrupt Control Register 2 (ICR2)..................................................................... 184
Interrupt Control Register 3 (ICR3)..................................................................... 185
PINT Interrupt Enable Register (PINTER).......................................................... 187
Interrupt Request Register 0 (IRR0) .................................................................... 187
Interrupt Request Register 1 (IRR1) .................................................................... 190
Interrupt Request Register 2 (IRR2) .................................................................... 191
Interrupt Sequence ............................................................................................... 197
Multiple Interrupts ............................................................................................... 199
Features................................................................................................................ 203
Block Diagram..................................................................................................... 204
Register Configuration......................................................................................... 205
Break Address Register A (BARA) ..................................................................... 206
Break Address Mask Register A (BAMRA)........................................................ 206
Break Bus Cycle Register A (BBRA).................................................................. 207
Break Address Register B (BARB)...................................................................... 209
Break Address Mask Register B (BAMRB) ........................................................ 210
Break Data Register B (BDRB) ........................................................................... 211
Break Data Mask Register B (BDMRB).............................................................. 212
Break Bus Cycle Register B (BBRB) .................................................................. 213
Break Control Register (BRCR) .......................................................................... 215
..................................................................................... 203