HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 754

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 USB Function Controller
Bit 7—Bus Reset (BRST): Set to 1 when the bus reset signal is detected on the USB bus.
Bit 6—EP1 FIFO Full (EP1 FULL): This bit is set when endpoint 1 receives one packet of data
normally from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer.
EP1 FULL is a status bit, and cannot be cleared.
Bit 5—EP2 Transfer Request (EP2 TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 4—EP2 FIFO Empty (EP2 EMPTY): This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be written. EP2 EMPTY is a status bit, and
cannot be cleared.
Bit 3—Setup Command Receive Complete (SETUP TS): This bit is set to 1 when endpoint 0
receives normally a setup command requiring decoding on the application side, and returns an
ACK handshake to the host.
Bit 2—EP0o Receive Complete (EP0o TS): This bit is set to 1 when endpoint 0 receives data
from the host normally, stores the data in the FIFO buffer, and returns an ACK handshake to the
host.
Bit 1—EP0i Transfer Request (EP0i TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 0—EP0i Transmit Complete (EP0i TS): This bit is set when data is transmitted to the host
from endpoint 0 and an ACK handshake is returned.
Rev.6.00 Mar. 27, 2009 Page 696 of 1036
REJ09B0254-0600
Initial value:
R/W:
Bit:
BRST
R/W
7
0
FULL
EP1
R
6
0
EP2
R/W
TR
5
0
EMPTY
EP2
R
4
1
SETUP
R/W
TS
3
0
EP0o
R/W
TS
2
0
EP0i
R/W
TR
1
0
EP0i
R/W
TS
0
0