HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 632

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.6
The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial
clock output in the asynchronous mode, enables/disables interrupt requests, and selects the
transmit/receive clock source. The CPU can always read and write the SCSCR2. The SCSCR2 is
initialized to H'00 by a reset or in standby and module standby modes.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-FIFO-data-empty
interrupt (TXI) requested when serial transmit data is transferred from transmit FIFO data register
2 (SCFTDR2) to transmit shift register 2 (SCTSR2), when the quantity of data in transmit FIFO
register 2 becomes less than the specified number of transmission triggers, and when the TDFE
flag in serial status register 2 (SCSSR2) is set to1.
Bit 7: TIE
0
1
Note: * The TXI interrupt request can be cleared by writing the greater quantity of transmit data
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and
receive-error (ERI) interrupts requested when serial receive data is transferred from receive shift
register 2 (SCRSR2) to receive FIFO data register 2 (SCFRDR2), when the quantity of data in
receive FIFO register 2 becomes more than the specified number of receive triggers, and when the
RDRF flag in SCSSR2 is set to1.
Bit 6: RIE
0
1
Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it
Rev.6.00 Mar. 27, 2009 Page 574 of 1036
REJ09B0254-0600
Initial value:
than the specified number of transmission triggers to SCFTDR2 and by clearing TDFE to 0
after reading 1 from TDFE, or can be cleared by clearing TIE to 0.
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. At RDF, read 1 from
the RDF flag and clear it to 0, after reading the received data from SCFRDR2 until the
quantity of received data becomes less than the specified number of the receive triggers.
Serial Control Register 2 (SCSCR2)
R/W:
Bit:
Description
Transmit-FIFO-data-empty interrupt request (TXI) is disabled.*
Transmit-FIFO-data-empty interrupt request (TXI) is enabled
Description
Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break
interrupt (BRI) requests are disabled.*
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled.
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
R/W
RE
4
0
—
R
3
0
—
R
2
0
CKE1
R/W
0
1
(Initial value)
(Initial value)
CKE0
R/W
0
0