HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 634

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.7
Serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of
receive errors in the data of receive FIFO data register 2, and the lower 8 bits indicate SCIF
operating state.
The CPU can always read and write the SCSSR2, but cannot write 1 in the status flags (ER,
TEND, TDFE, BRK, RDF, and DR). These flags can be cleared to 0 only if they have first been
read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits that cannot be written. The
SCSSR2 is initialized to H'0060 by a reset or in standby and module standby modes.
Note: * The only value that can be written is 0 to clear the flag.
Bit 7—Receive Error (ER): Indicates that a parity error has occurred when received data
includes a framing error or a parity.
Bit 7: ER
0
1
Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not affect the ER bit, which retains its
Rev.6.00 Mar. 27, 2009 Page 576 of 1036
REJ09B0254-0600
Lower 8 bits:
Initial value:
2. In the stop mode, only the first stop bit is checked; the second stop bit is not checked.
Serial Status Register 2 (SCSSR2)
previous value. Even if a receive error occurs, the received data is transferred to
SCFRDR2 and the receive operation is continued. Whether or not the data read from
SCFRDR2 includes a receive error can be detected by the FER and PER bits of
SCSSR2.
R/W:
Description
Receive is in progress, or receive is normally completed. *
ER is cleared to 0 when the chip is reset or enters standby mode, or when 0 is
written after 1 is read from ER.
A framing error or a parity error has occurred.
ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit
of the received data is 1 at the end of one-data receive *
number of 1's in the received data and in the parity bit does not match the
even/odd parity specification specified by the O/E bit of the SCSMR2.
R/(W)*
ER
7
0
R/(W)*
TEND
6
1
R/(W)*
TDFE
5
1
R/(W)*
BRK
4
0
FER
R
3
0
PER
2
R
2
0
, or when the total
1
R/(W)*
RDF
0
1
(Initial value)
R/(W)*
DR
0
0