HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 925

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

28.4
The A/D converter operates by successive approximations with 10-bit resolution. It has three
operating modes: single mode, multi mode, and scan mode.
28.4.1
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADF, then write 0 in ADF.
When the mode or analog input channel must be switched during A/D conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN2) is selected in single mode are described next.
Figure 28.3 shows a timing diagram for this example.
1. Single mode is selected (MULTI = 0), input channel AN2 is selected (CH2 = CH0 = 0, CH1 =
2. When A/D conversion is completed, the result is transferred into ADDRC. At the same time
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt processing routine starts.
5. The routine reads ADF, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRC = 0).
7. Execution of the A/D interrupt processing routine ends. Then, when the ADST bit is set to 1,
1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
A/D conversion starts to execute 2 to 7 above.
Operation
Single Mode (MULTI = 0)
Rev.6.00 Mar. 27, 2009 Page 867 of 1036
Section 28 A/D Converter
REJ09B0254-0600