HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 551

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 4: RE
0
1
Notes: 1. Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is
ignored in the clock synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
1
Note: * The SCI does not transfer receive data from the SCRSR to the SCRDR, does not detect
Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted.
Bit 2: TEIE
0
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register
1
2. Serial reception starts when a start bit is detected in the asynchronous mode, or
receive errors, and does not set the RDRF, FER, and ORER flags in the serial status
register (SCSSR). When it receives data that includes MPB = 1, the SCSSR’s MPB flag is
set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if
the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be
set.
(SCSSR) after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end
(TEND) bit to 0, or by clearing the TEIE bit to 0.
flags retain their previous values.
synchronous clock input is detected in the clock synchronous mode. Select the receive
format in the SCSMR before setting RE to 1.
Description
Receiver disabled *
Receiver enabled *
Description
Multiprocessor interrupts are disabled (normal receive operation)
[Clear conditions]
1. When MPIE is cleared to 0
2. When the multiprocessor bit (MPB) is set to 1 in receive data
Multiprocessor interrupts are enabled*
Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI),
and setting of the RDRF, FER, and ORER status flags in the serial status register
(SCSSR) are disabled until data with a multiprocessor bit of 1 is received.
Description
Transmit-end interrupt (TEI) requests are disabled*
Transmit-end interrupt (TEI) requests are enabled*
2
1
Section 17 Serial Communication Interface (SCI)
Rev.6.00 Mar. 27, 2009 Page 493 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)
(Initial value)