HD6417727F160V Renesas Electronics America, HD6417727F160V Datasheet - Page 25

• Manufacturer Part Number: HD6417727F160V
• Description: MPU 3V 16K PB-FREE 240-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F160V

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 160MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Bus State Controller (BSC)
12.1 Overview........................................................................................................................... 283
12.2 BSC Registers ................................................................................................................... 293
12.3 BSC Operation .................................................................................................................. 316
Section 13 Li Bus State Controller (LBSC)
13.1 Overview........................................................................................................................... 367
12.1.1 Features................................................................................................................ 283
12.1.2 Block Diagram..................................................................................................... 285
12.1.3 Pin Configuration................................................................................................. 286
12.1.4 Register Configuration......................................................................................... 287
12.1.5 Area Overview..................................................................................................... 288
12.1.6 PC Card Support .................................................................................................. 292
12.2.1 Bus Control Register 1 (BCR1) ........................................................................... 293
12.2.2 Bus Control Register 2 (BCR2) ........................................................................... 297
12.2.3 Wait State Control Register 1 (WCR1)................................................................ 298
12.2.4 Wait State Control Register 2 (WCR2)................................................................ 299
12.2.5 Individual Memory Control Register (MCR)....................................................... 303
12.2.6 PCMCIA Control Register (PCR)........................................................................ 306
12.2.7 Synchronous DRAM Mode Register (SDMR) .................................................... 310
12.2.8 Refresh Timer Control/Status Register (RTCSR)................................................ 311
12.2.9 Refresh Timer Counter (RTCNT)........................................................................ 313
12.2.10 Refresh Time Constant Register (RTCOR) ......................................................... 314
12.2.11 Refresh Count Register (RFCR) .......................................................................... 314
12.2.12 Cautions on Accessing Refresh Control Related Registers.................................. 315
12.3.1 Endian/Access Size and Data Alignment............................................................. 316
12.3.2 Description of Areas ............................................................................................ 322
12.3.3 Basic Interface ..................................................................................................... 325
12.3.4 Synchronous DRAM Interface............................................................................. 331
12.3.5 Burst ROM Interface............................................................................................ 347
12.3.6 PCMCIA Interface ............................................................................................... 350
12.3.7 Waits between Access Cycles.............................................................................. 362
12.3.8 Bus Arbitration .................................................................................................... 363
12.3.9 Bus Pull-Up.......................................................................................................... 364
13.1.1 Features................................................................................................................ 367
13.1.2 Register Configuration......................................................................................... 367
13.1.3 Bus Control Register 1 (BCR1) ........................................................................... 368
13.1.4 Bus Control Register 2 (BCR2) ........................................................................... 370
13.1.5 Wait State Control Register 1 (WCR1)................................................................ 371
13.1.6 Wait State Control Register 2 (WCR2)................................................................ 372
13.1.7 Individual Memory Control Register (MCR)....................................................... 373
......................................................................... 283
................................................................. 367
Rev.6.00 Mar. 27, 2009 Page xxiii of lvi
REJ09B0254-0600