HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 112
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 3 Memory Management Unit (MMU)
3.3.2
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits in PTEH 4 to 0 are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 0, VPN bits 16 to 12 alone are used as the index number
2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
The second method is used to prevent lowered TLB efficiency that results when multiple
processes run simultaneously in the same virtual address space (multiple virtual memory) and a
specific entry is selected by indexing of each process. Figures 3.5 and 3.6 show the indexing
schemes.
Rev. 5.00 May 29, 2006 page 62 of 698
REJ09B0146-0500
number
TLB Indexing
31
0
Virtual address
31
VPN(31–17)
Index
VPN(11, 10)
17
Address array
Figure 3.5 TLB Indexing (IX = 1)
16
12
11
ASID(7–0)
0
Exclusive-OR
V
Ways 0 to 3
PTEH register
PPN(3–0)
31
VPN
PR(1, 0) SZ C
Data array
ASID(4 to 0)
10
0
D SH
7
ASID
0
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