HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 40

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Figure 9.21
Figure 9.22
Figure 9.23
Figure 9.24
Figure 9.25
Figure 9.26
Figure 9.27
Figure 9.28
Figure 9.29
Figure 9.30
Section 10 Clock Pulse Generator (CPG)
Figure 10.1
Figure 10.2
Figure 10.3
Section 11 Watchdog Timer (WDT)
Figure 11.1
Figure 11.2
Section 12 Timer Unit (TMU)
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 12.8
Figure 12.9
Section 13 Realtime Clock (RTC)
Figure 13.1
Figure 13.2(a) Setting the Time................................................................................................... 357
Figure 13.2(b) Setting the Time................................................................................................... 357
Rev. 5.00 May 29, 2006 page xxxviii of xlviii
Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)..................................... 286
Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)..................................... 286
Cycle-Steal Mode, Level input
(CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) ......................................... 286
Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) 287
Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles)...................................... 287
Burst Mode, Level Input ...................................................................................... 287
Burst Mode, Edge Input....................................................................................... 288
Source Address Reload Function Diagram .......................................................... 288
Timing Chart of Source Address Reload Function .............................................. 289
CMT Block Diagram ........................................................................................... 292
Counter Operation................................................................................................ 295
Count Timing....................................................................................................... 296
CMF Set Timing .................................................................................................. 297
Timing of CMF Clear by the CPU....................................................................... 297
Block Diagram of Clock Pulse Generator............................................................ 304
Points for Attention when Using Crystal Oscillator............................................. 313
Points for Attention when Using PLL Oscillator Circuit ..................................... 314
Block Diagram of the WDT................................................................................. 315
Writing to WTCNT and WTCSR ........................................................................ 319
TMU Block Diagram ........................................................................................... 324
Setting the Count Operation................................................................................. 333
Auto-Reload Count Operation ............................................................................. 334
Count Timing when Internal Clock Is Operating................................................. 334
Count Timing when External Clock Is Operating (Both Edges Detected)........... 335
Count Timing when On-Chip RTC Clock Is Operating ...................................... 335
Operation Timing when Using the Input Capture Function
(Using TCLK Rising Edge) ................................................................................. 336
UNF Set Timing................................................................................................... 337
Status Flag Clear Timing ..................................................................................... 337
RTC Block Diagram ............................................................................................ 340