HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 240
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 8 Bus State Controller (BSC)
8.4.6
The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the timing for the
assertion or negation of the OE and WE signals for the PCMCIA interface connected to areas 5
and 6. The width for assertion of the OE and WE signals is set by the wait control bit in the WCR2
register.
Rev. 5.00 May 29, 2006 page 190 of 698
REJ09B0146-0500
Bit *
15
14
13, 12
11
7
6
PCMCIA Control Register (PCR)
Bit Name
A6W3
A5W3
—
A5TED2
A5TED1
A5TED0
Initial Value
0
0
All 0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Area 6 Wait Control
The A6W3 bit specifies the number of inserted
wait states for area 6 combined with bits A6W2 to
A6W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0
when area 6 is not set to PCMCIA.
Refer to table 8.10 for details.
Area 5 Wait Control
The A5W3 bit specifies the number of inserted
wait states for area 5 combined with bits A5W2 to
A5W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0
when area 5 is not set to PCMCIA.
The relationship between the setting value and the
number of waits is the same as A6W3.
Reserved
These bits are always read as 0. The write value
should always be 0.
Area 5 Address OE/WE Assert Delay
The A5TED bits specify the address to OE/WE
assert delay time for the PCMCIA interface
connected to area 5.
000: 0.5-cycle delay
001: 1.5-cycle delay
010: 2.5-cycle delay
011: 3.5-cycle delay
100: 4.5-cycle delay
101: 5.5-cycle delay
110: 6.5-cycle delay
111: 7.5-cycle delay
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