HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 601
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Part Number:
HD6417706F133
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD6417706F133V
Manufacturer:
EDISON
Quantity:
2 000
Company:
Part Number:
HD6417706F133V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417706F133V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 601 of 751
- Download datasheet (5Mb)
Legend:
Bit
7
6
5
4 to
0
Bit Name
DAOE1
DAOE0
DAE
—
: Don’t care
Initial Value
0
0
0
All 1
R/W
R/W
R/W
R/W
R
Description
D/A Output Enable 1
Controls D/A conversion and analog output.
0: DA1 analog output is disabled
1: Channel-1 D/A conversion and DA1 analog output
D/A Output Enable 0
Controls D/A conversion and analog output.
0: DA0 analog output is disabled
1: Channel-0 D/A conversion and DA0 analog output
D/A Enable
Controls D/A conversion, together with bits DAOE0 and
DAOE1. When the DAE bit is cleared to 0, D/A
conversion is controlled independently in channels 0
and 1. When this LSI enters standby mode while D/A
conversion is enabled, the D/A output is held and the
analog power-supply current is equivalent to that during
D/A conversion. To reduce the analog power-supply
current in standby mode, clear the DAOE0 and DAOE1
bits and disable the D/A output.
00 : D/A conversion is disabled in channels 0 and 1
010: D/A conversion is enabled in channel 0
011: D/A conversion is enabled in channels 0 and 1
100: D/A conversion is disabled in channel 0
101: D/A conversion is enabled in channels 0 and 1
11 : D/A conversion is enabled in channels 0 and 1
When the DAE bit is set to 1, even if bits DAOE0 and
DAOE1 in DACR and the ADST bit in ADCSR are
cleared to 0, the same current is drawn from the analog
power supply as during A/D and D/A conversion.
Reserved
These bits are always read as 1. The write value should
always be 1.
are enabled
are enabled
D/A conversion is disabled in channel 1
D/A conversion is enabled in channel 1
Rev. 5.00 May 29, 2006 page 551 of 698
Section 20 D/A Converter (DAC)
REJ09B0146-0500
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