HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 149

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.1
5.1.1
The cache uses a 4-way set associative system. It is composed of four ways (banks), each of which
is divided into an address section and a data section. Each of the address and data sections is
divided into 256 entries. The data section of the entry is called a line. Each line consists of 16
bytes (4 bytes
16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure.
Instruction/data mixed, 16-byte cache
256 entries/way, 4-way set associative, 16-byte block
Write-back/write-through selectable
LRU replacing algorithm
1-stage write-back buffer
A maximum of two ways lockable
Entry 255
Entry 0
Entry 1
Feature
Cache Structure
.
.
.
.
.
.
24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
4). The data capacity per way is 4 kbytes (16 bytes
Figure 5.1 Cache Structure
Section 5 Cache
255
0
1
.
.
.
.
.
.
LW0
LW0 to LW3: Longword data 0 to 3
128 (32
LW1
Rev. 5.00 May 29, 2006 page 99 of 698
4) bits
LW2
Data array (ways 0 to 3)
LW3
256 entries), with a total of
REJ09B0146-0500
Section 5 Cache
255
0
1
.
.
.
.
.
.
LRU
6 bits