HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 318

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request: In this mode a transfer is performed at the transfer request
signal (interrupt request signal) of an on-chip peripheral module. This mode cannot be set in case
of 16-byte transfer. The transfer request signals include 4 signals: the receive data full interrupts
(RXI) and the transmit data empty interrupts (TXI) from serial communication interfaces (SCIF),
the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer
interrupt (CMI) of the CMT. When this mode is selected, if the DMA transfer is enabled (DE = 1,
DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request
signal. The source of the transfer request does not have to be the data transfer source or
destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's
receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source
must be the SCI's transmit data register (TDR). And if the transfer requester is the A/D converter,
the data transfer source must be the A/D data register (ADDR).
Table 9.3
Legend:
ADDR: A/D data register of A/D converter
Note:
When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt
enable bits must be set to output the interrupt signals.
If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request
signal, an interrupt is not generated to the CPU.
Rev. 5.00 May 29, 2006 page 268 of 698
REJ09B0146-0500
RS3 RS2
1
1
1
1
1
1
0
0
1
1
1
1
* External memory, memory-mapped external device, on-chip peripheral module
(excluding DMAC, UBC, and BSC)
RS1
1
1
0
0
1
1
Selecting On-Chip Peripheral Module Request Modes with the RS Bit
RS0
0
1
0
1
0
1
DMA
Transfer
Request
Source
SCIF
transmitter
SCIF
receiver
A/D
converter
CMT
DMA Transfer Request
Signal
TXI2 (SCIF transmit data
empty interrupt transfer
request)
RXI2 (SCIF receive data full
interrupt transfer request)
ADI (A/D conversion end
interrupt)
CMI (Compare match timer
interrupt)
Source
Any *
RDR1
ADDR
Any *
Desti-
nation Bus Mode
TDR2
Any *
Any *
Any *
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal
Burst/
cycle steal