HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 230

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Bus State Controller (BSC)
Rev. 5.00 May 29, 2006 page 180 of 698
REJ09B0146-0500
Bit
15
14
13
12
11
10
9
8
Bit Name
WAITSEL
—
A6IW1
A6IW0
A5IW1
A5IW0
A4IW1
A4IW0
Initial Value
0
0
1
1
1
1
1
1
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
WAIT Sampling Timing Select
Specifies the WAIT signal sampling timing.
0: Set 1 to use the WAIT signal.
1: The WAIT signal is sampled at the falling edge of
Reserved
These bits are always read as 0. The write value
should always be 0.
Area 6 Intercycle Idle Specification
Specify the number of idles inserted between bus
cycles when switching between physical space area
6 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
Area 5 Intercycle Idle Specification
Specify the number of idles inserted between bus
cycles when switching between physical space area
5 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
Area 4 Intercycle Idle Specification
Specify the number of idles inserted between bus
cycles when switching between physical space area
4 to another space or between a read access to a
write access in the same physical space.
00: 1 idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 3 idle cycles inserted
CKIO.