HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 314

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 Direct Memory Access Controller (DMAC)
Note:
Rev. 5.00 May 29, 2006 page 264 of 698
REJ09B0146-0500
Bit
1
0
* Only 0 can be written to the AE and NMIF bits after 1 is read.
Bit Name
NMIF
DME
Initial Value
0
0
R/W
R/(W) * NMI Flag
R/W
Description
NMIF indicates that an NMI interrupt occurred.
This bit is set regardless of whether DMAC is in
operating or halt state. If this bit is set during data
transfer, the transfer on all channels are
suspended. The CPU cannot write 1 to this bit.
Only 0 can be written to clear this bit after 1 is
read.
0: No NMI input. DMA transfer is enabled. (Initial
1: NMI input. DMA transfer is disabled.
DMA Master Enable
DME enables or disables DMA transfers on all
channels. If the DME bit and the DE bit
corresponding to each channel in CHCR are set to
1s, transfer is enabled in the corresponding
channel. If this bit is cleared during transfer,
transfers on all the channels can be suspended.
Even if the DME bit is set, transfer is not enabled
if the TE bit is 1 or the DE bit is 0 in CHCR, or the
AE bit is 1 or the NMIF bit is 1 in DMAOR.
0: Disable DMA transfers on all channels
1: Enable DMA transfers on all channels
value)
Clearing condition: Writing NMIF = 0 after NMIF
= 1 read, power-on reset, manual reset
Setting condition: This bit is set by occurrence
of an NMI interrupt.