HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 166
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Section 6 Interrupt Controller (INTC)
It is possible to wake the chip up from the software standby state with an NMI interrupt (except
when the MAI bit of the ICR1 register is set to 1).
6.3.2
IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority
level can be set by priority setting registers C to D (IPRC to IPRD) in a range from levels 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit. It is not necessary to clear the bit to 0
when using level-sensing. Instead, the pin corresponding to the interrupt request must be driven
high.
When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the
pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask
after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0).
It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle
width by peripheral clock (P ) basis.
In level detection, keep the level until the CPU accepts an interrupt and starts the interrupt
processing.
The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt
processing.
Interrupts IRQ4 to IRQ0 can wake the chip up from the software standby state when the relevant
interrupt level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator
is used).
Notes: When the IRQ is used in edge sensitive, pay attention to the following:
Rev. 5.00 May 29, 2006 page 116 of 698
REJ09B0146-0500
1. If an IRQ edge is input immediately before the CPU enters standby mode (the period
2. If an IRQ edge is input while the frequency is changed by the FRQCR STC bit (when
IRQ Interrupt
between the SLEEP instruction executed by the CPU to high level of STATUS0), an
interrupt may not be detected. In this case, when an IRQ edge is input again after
STATUS0 becomes high level, an interrupt is detected.
the WDT is counting), an interrupt may not be detected. In this case, when an IRQ
edge is input again after the WDT halts counting, an interrupt is detected.
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