HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 359
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Price
Part Number:
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Quantity:
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Part Number:
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Manufacturer:
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20 000
- Current page: 359 of 751
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Notes: 1. This LSI cannot operate in an FRQCR value other than that listed in table 10.3.
Cautions:
1. The input to divider 1 is the output of the PLL circuit 1:
2. The input of divider 2 is the output of the PLL circuit 1.
3. The frequency of the CPU clock (I ):
4. The frequency of the peripheral clock (P ):
5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
Clock
Mode FRQCR *
7
multiplication ratio of PLL circuit 1.
H'0100
H'0101
H'0102
H'0111
H'0112
H'0115
H'0116
H'0122
H'0126
H'012A
H'A100
H'A101
H'E100
H'E101
2. Taking input clock as 1
When PLL circuit 1 is on.
The frequency of the CPU clock (I ) is the product of the frequency of the CKIO pin,
the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1
when PLL circuit 1 is on.
Do not set the CPU clock frequency lower than the CKIO pin frequency.
The frequency of the peripheral clock (P ) is the product of the frequency of the CKIO
pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2.
The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, or higher than 33 MHz.
Max. frequency: I = 133.34 MHz, B (CKIO) = 66.67 MHz, P = 33.34 MHz
1
PLL1
ON ( 1)
ON ( 1)
ON ( 1)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 2)
ON ( 4)
ON ( 4)
ON ( 4)
ON ( 3)
ON ( 3)
ON ( 3)
ON ( 3)
PLL2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
1:1:1
1:1:1/2
1:1:1/4
2:1:1
2:1:1/2
1:1:1
1:1:1/2
4:1:1
2:1:1
1:1:1
3:1:1
3:1:1/2
1:1:1
1:1:1/2
Clock Rate *
(I:B:P)
2
Input Frequency Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 44.44 MHz
25 MHz to 33.34 MHz
25 MHz to 44.44 MHz
Section 10 Clock Pulse Generator (CPG)
Rev. 5.00 May 29, 2006 page 309 of 698
CKIO Frequency
Range
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 66.67 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 33.34 MHz
25 MHz to 44.44 MHz
25 MHz to 33.34 MHz
25 MHz to 44.44 MHz
REJ09B0146-0500
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