HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 239

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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Bit
2
1
0
Bit Name
RFSH
RMODE
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Refresh Control
The RFSH bit determines whether or not the refresh
operation of the DRAM and synchronous DRAM is
performed. The timer for generation of the refresh
request frequency can also be used as an interval
timer.
0: No refresh
1: Refresh
Refresh Mode
The RMODE bit selects whether to perform an
ordinary refresh or a self-refresh when the RFSH bit
is 1. When the RFSH bit is 1 and this bit is 0, a CAS-
before-RAS refresh or an auto-refresh is performed
on synchronous DRAM at the period set by the
refresh-related registers RTCNT, RTCOR and
RTCSR. When a refresh request occurs during an
external bus cycle, the bus cycle will be ended and
the refresh cycle performed. When the RFSH bit is 1
and this bit is also 1, the synchronous DRAM will
wait for the end of any executing external bus cycle
before going into a self-refresh. All refresh requests
to memory that is in the self-refresh state are
ignored.
0: CAS-before-RAS refresh (RFSH must be 1)
1: Self-refresh (RFSH must be 1)
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 5.00 May 29, 2006 page 189 of 698
Section 8 Bus State Controller (BSC)
REJ09B0146-0500

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