HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 433

IC SUPERH MPU ROMLESS 176LQFP

HD6417706F133

Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417706F133

Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

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14.3.10 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator
clock source selected by the CKS1 and CKS0 bits in SCSMR, determines the serial
transmit/receive bit rate.
The CPU can always read and write the SCBRR. The SCBRR is initialized to H'FF by a reset or in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in two channels.
The SCBRR setting is calculated as follows:
Table 14.2 SCSMR Settings
Find the bit rate error for the asynchronous mode by the following formula:
n
0
1
2
3
Asynchronous mode: N
Clock synchronous mode: N
B:
N:
P : Operating frequency for peripheral modules (MHz)
n:
Error (%) =
Baud rate generator clock source (n
n, see table 14.2.)
Bit rate (bit/s)
SCBRR setting for baud rate generator (0
(N + 1)
Clock Source
P
P /4
P /16
P /64
B
[P /(64
10
64
6
[P /(8
2
2n 1
2
2n – 1
2
Section 14 Serial Communication Interface (SCI)
1
2n – 1
CKS1
0
0
1
1
0, 1, 2, 3) (for the clock sources and values of
B)]
100
B)]
Rev. 5.00 May 29, 2006 page 383 of 698
N
10
6
255)
10
– 1
6
SCSMR Settings
– 1
CKS0
0
1
0
1
REJ09B0146-0500

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