HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 281

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3. Relationship between Refresh Requests and Bus Cycle Requests
When using synchronous DRAM, use the following procedure to initiate self-refreshing.
1. Clear the refresh control bit to 0.
2. Write H'00 to the RTCNT register.
3. Set the refresh control bit and refresh mode bit to 1.
If a refresh request is generated during execution of a bus cycle, execution of the refresh is
deferred until the bus cycle is completed. If a refresh request occurs when the bus has been
released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match
between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new
refresh request is generated, the previous refresh request is eliminated. In order for refreshing
to be performed normally, care must be taken to ensure that no bus cycle or bus mastership
occurs that is longer than the refresh interval. When a refresh request is generated, the
IRQOUT pin is asserted (driven low). Therefore, normal refreshing can be performed by
having the IRQOUT pin monitored by a bus master other than this LSI requesting the bus, or
the bus arbiter, and returning the bus to this LSI. When refreshing is started, and if no other
interrupt request has been generated, the IRQOUT pin is negated (driven high).
RASU, RASL
CASU, CASL
RD/WR
CKIO
CKE
CSn
Figure 8.26 Synchronous DRAM Self-Refresh Timing
Tp
TRs1
(TRs2)
Rev. 5.00 May 29, 2006 page 231 of 698
Section 8 Bus State Controller (BSC)
(TRs2)
TRs3
(Tpc)
REJ09B0146-0500
(Tpc)