HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 362

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Clock Pulse Generator (CPG)
10.5
The frequency of the CPU clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of
these are controlled by software through the frequency control register. The methods are described
below.
10.5.1
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The on-
chip WDT counts the settling time. Refer to section 11, Watchdog Timer (WDT), for more details.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
3. Set the desired value in the STC2, STC1 and STC0 bits. The division ratio can also be set in
4. The processor pauses internally and the WDT starts incrementing. At this time, the CPU (I )
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
10.5.2
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC2 to IFC0
2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values
3. The clock is immediately supplied at the new division ratio.
Rev. 5.00 May 29, 2006 page 312 of 698
REJ09B0146-0500
WDT. The following must be set:
WTCSR register TME bit
WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock
WTCNT counter: Initial counter value
the IFC2 to IFC0 bits and PFC2 to PFC0 bits.
and peripheral clocks (P ) both stop, and the clock is continuously output to the CKIO pin in
clock modes 0 to 2.
operating again. The WDT stops after it overflows.
that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note
that if the wrong value is set, the processor will malfunction.
Operation
Changing the Multiplication Rate
Changing the Division Ratio
0: WDT stops
000 and PFC2 to PFC0
010.