HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 470
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Part Number:
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Quantity:
20 000
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Part Number:
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Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
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Quantity:
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Part Number:
HD6417706F133V
Manufacturer:
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Quantity:
20 000
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Section 14 Serial Communication Interface (SCI)
The receive margin in the asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
Where: M
From equation 1, if F
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.
Cautions for Clock Synchronous External Clock Mode:
Caution for Clock Synchronous Internal Clock Mode: In the receiving, RDRF become 1 when
RE is set to 0, 1.5 clocks after the rising edge of the SCK0 output of the D7 bit in RxD0, but it
cannot be copied to SCRDR.
Rev. 5.00 May 29, 2006 page 420 of 698
REJ09B0146-0500
Set TE = RE = 1 only when the external clock SCK0 is 1.
Do not set TE = RE = 1 until at least four clocks after the external clock SCK0 has changed
from 0 to 1.
When receiving, RDRF is 1 when RE is set to zero 2.5–3.5 clocks after the rising edge of the
SCK0 input of the D7 bit in RxD0, but it cannot be copied to SCRDR.
M = 0.5 –
N
D
L
F
M
Absolute deviation of clock frequency
Frame length (L
Ratio of clock frequency to bit rate (N
Clock duty cycle (D
Receive margin ( )
(0.5 – 1/(2
46.875
2N
1
0 and D
– (L – 0.5)F –
16))
9 to 12)
100
0.5, the receive margin is 46.875%, as in equation 2.
0 to 1.0)
D – 0.5
N
(1 + F)
16)
100%
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