HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 13
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Item
6.4.4 Interrupt
Request Register 0
(IRR0)
8.1 Feature
8.4.4 Wait State
Control Register 2
(WCR2)
Table 8.6 Area 6 Wait
Control (Normal
Memory I/F)
Table 8.7 Area 5 Wait
Control (Normal
Memory I/F)
Page
130
163
182
184
184
Revision (See Manual for Details)
Table amended
(Before) • PCMCIA direct-connection interface
(After) • PCMCIA interface
Description amended
Table title amended
Table title amended
Bit
2
1
0
Bit
15
14
13
12
11
10
Bit Name
IRQ2R
IRQ1R
IRQ0R
Bit Name
A6W2
A6W1
A6W0
A5W2
A5W1
A5W0
Initial Value R/W
0
0
0
Initial Value R/W
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 May 29, 2006 page xi of xlviii
Description
IRQ2 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ2 pin. When edge detection mode is set for IRQ2,
an interrupt request is cleared by clearing the IRQ2R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ2 pin.
0: An interrupt request is not input to IRQ2 pin
1: An interrupt request is input to IRQ2 pin
IRQ1 Interrupt Request
Indicates whether an interrupt request is input to the
IRQ1 pin. When edge detection mode is set for IRQ1,
an interrupt request is cleared by clearing the IRQ1R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ1 pin.
0: An interrupt request is not input to IRQ1 pin
1: An interrupt request is input to IRQ1 pin
IRQ0 Interrupt Request (IRQ0R)
Indicates whether an interrupt request is input to the
IRQ0 pin. When edge detection mode is set for IRQ0,
an interrupt request is cleared by clearing the IRQ0R
bit. It is not necessary to clear the flag when using
level-sensing, because this bit merely shows the status
of the IRQ0 pin.
0: An interrupt request is not input to IRQ0 pin
1: An interrupt request is input to IRQ0 pin
Description
Area 6 Wait Control
Specify the number of wait states inserted into
physical space area 6 in combination with A6W3 in
PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.6 for details.
Area 5 Wait Control
Specify the number of wait states inserted into
physical space area 5 in combination with A5W3 in
PCR. Also specify the burst pitch for burst transfer.
Refer to table 8.7 for details.
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