HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 19
HD6417706F133
Manufacturer Part Number
HD6417706F133
Description
IC SUPERH MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417706F133V.pdf
(751 pages)
Specifications of HD6417706F133
Core Processor
SH-3
Core Size
32-Bit
Speed
133MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.75 V ~ 2.05 V
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
176-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Manufacturer
Quantity
Price
Part Number:
HD6417706F133
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD6417706F133V
Manufacturer:
EDISON
Quantity:
2 000
Company:
Part Number:
HD6417706F133V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417706F133V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Item
14.3.8 SC Port
Control Register
(SCPCR)
16.1 Feature
Figure 16.1 SCIF
Block Diagram
16.3.6 Serial Control
Register 2 (SCSCR2)
16.4.1 Serial
Operation
Serial data reception:
Page
381
442
451
479
Revision (See Manual for Details)
Table amended
Figure amended
Bit table amended
Description amended
5. When modem control is enabled, the RTS2 signal is output
when SCFRDR2 is full. ...
Bit
1
0
SCK2
Bit
11
10
9
8
7
6
5
4
RTS2
CTS2
RxD2
TxD2
Bit Name
CKE1
CKE0
Bit Name
SCP5MD1
SCP5MD0
SCP4MD1
SCP4MD0
SCP3MD1
SCP3MD0
SCP2MD1
SCP2MD0
(16 stages)
SCFRDR2
SCRSR2
Initial
Value
0
0
Initial Value
1
0
1
0
1
0
0
0
R/W
R/W
R/W
Rev. 5.00 May 29, 2006 page xvii of xlviii
(16 stages)
SCFTDR2
Parity generation
SCTSR2
00: Internal clock, SCK pin used for I/O pin (input signal is
01: Internal clock, SCK2 pin used for clock output *
10: External clock, SCK2 pin used for clock input *
11: External clock, SCK2 pin used for clock input *
Notes: 1. The output clock frequency is 16 times the bit
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Parity check
ignored)
2. The input clock frequency is 16 times the bit rate.
Description
See section 17.1.10, SC Port Control Register
(SCPCR).
rate.
Transmit/
receive
SCSMR2
control
SCSCR2
SCFDR2
SCFCR2
SCSSR2
SCPCR
SCPDR
Ex
2
2
1
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