HD6417706F133 Renesas Electronics America, HD6417706F133 Datasheet - Page 253

• Manufacturer Part Number: HD6417706F133
• Description: IC SUPERH MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417706F133

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.75 V ~ 2.05 V
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 176-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR
signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and
addresses multiplexed. Control of RASU, RASL, CASU, CASL, data timing, and address
multiplexing is set with MCR.
Area 3: Area 3 physical addresses A28 to A26 are 011. Addresses A31 to A29 are ignored and the
address range is H'0C000000 + H'20000000
n
Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to
this space. Byte, word or longword can be selected as the bus width using the A3SZ1 to A3SZ0
bits of BCR2 for ordinary memory.
When area 3 space is accessed, CS3 is asserted.
When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to
WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and
3 wait cycles using the A3W1 to A3W0 bits of WCR2.
When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR
signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and
addresses multiplexed. Control of RAS, CAS, and data timing and of address multiplexing is set
with MCR.
Area 4: Area 4 physical addresses A28 to A26 are 100. Addresses A31 to A29 are ignored and the
address range is H'10000000 + H'20000000
n
Only ordinary memories like SRAM and ROM can be connected to this space. Byte, word, or
longword can be selected as the bus width using the A4SZ1 to A4SZ0 bits of BCR2. When the
area 4 space is accessed, a CS4 signal is asserted. An RD signal that can be used as OE and the
WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected
between 0 and 10 wait cycles using the A4W2 to A4W0 bits of WCR2.
Area 5: Area 5 physical addresses A28 to A26 are 101. Addresses A31 to A29 are ignored and the
address range is the 64 Mbytes at H'14000000 + H'20000000
n (n
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range comprises the 32 Mbytes at H'14000000 + H'20000000
H'20000000
1 to 6 are the shadow spaces).
1 to 6 are the shadow spaces).
0 to 6 and n
n (where n = 0 to 6, and n = 1 to 6 represents shadow space), and the I/O card
1 to 6 are the shadow spaces).
n to H'13FFFFFF + H'20000000
n to H'0FFFFFFF + H'20000000
Rev. 5.00 May 29, 2006 page 203 of 698
Section 8 Bus State Controller (BSC)
n to H'17FFFFFF + H'20000000
n to H'15FFFFFF +
REJ09B0146-0500
n (n
n (n
0 to 6 and
0 to 6 and