EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 112

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

DSP Block Resource Descriptions
5–12
Stratix III Device Handbook, Volume 1
Every DSP block has nine 18-bit data input register banks per half DSP
block. Every half DSP block has the option to use the eight data register
banks as inputs to the four multipliers. The special ninth register bank is
a delay register required by modes that use both the cascade and chainout
features of the DSP block and is for balancing the latency requirements
when using the chained cascade feature.
A feature of the input register bank is to support a tap delay line.
Therefore, the top leg of the multiplier input (A) can be driven from
general routing or from the cascade chain, as shown in
Altera Corporation
Figure
October 2007
5–7.