EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 308

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–19. Stratix III Dynamic OCT Control Block
Note to
(1)
8–38
Stratix III Device Handbook, Volume 1
Write clock comes from either the PLL or the write leveling delay chain.
Figure
8–19:
f
group after sweeping all the available clocks in the write calibration
process. The DQ clock output is –90° phase-shifted compared to the DQS
clock output.
Similarly, the resynchronization clock feeds the read-leveling circuitry to
produce the optimal resynchronization and postamble clock for each
DQS/DQ group in the calibration process. The resynchronization and the
postamble clocks can use different clock outputs from the leveling
circuitry. The output from the read-leveling circuitry can also generate
the half-rate resynchronization clock that goes to the FPGA fabric.
1
Dynamic On-Chip Termination Control
Figure 8–19
the registers needed to dynamically turn on OCT during a read and turn
OCT off during a write.
For more information refer to section
Stratix III Device I/O Features
Handbook.
OCT Control Path
OCT Control
OCT Half-
Rate Clock
2
The ALTMEMPHY megafunction calibrates the alignment for
read and write leveling dynamically during the initialization
process.
shows the dynamic OCT control block. The block includes all
HDR
Block
DFF
Write
Clock (1)
Resynchronization
Registers
DFF
chapter in volume 1 of the Stratix III Device
OCT Enable
“OCT” on page
8–43, or to the
Altera Corporation
November 2007