EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 447

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

IEEE Std. 1149.1
BST Operation
Control
Altera Corporation
November 2007
Note to
(1)
SAMPLE / PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
HIGHZ
CLAMP
ICR instructions
PULSE_NCONFIG
CONFIG_IO
Table 13–4. Stratix III JTAG Instructions
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of
Table
(1)
(1)
(1)
13–4:
00 0000 0101 Allows a snapshot of signals at the device pins to be captured and
00 0000 1111 Allows the external circuitry and board-level interconnects to be tested
11 1111 1111 Places the 1-bit bypass register between the
00 0000 0111 Selects the 32-bit
00 0000 0110 Selects the
00 0000 1011 Places the 1-bit bypass register between the
00 0000 1010 Places the 1-bit bypass register between the
—
00 0000 0001 Emulates pulsing the
00 0000 1101 Allows I/O reconfiguration through JTAG ports using the IOCSR for
Instruction
Stratix III devices support the IEEE Std. 1149.1 (JTAG) instructions shown
in
Code
Table
13–4.
examined during normal device operation, and permits an initial data
pattern to be output at the device pins. Also used by the SignalTap
embedded logic analyzer.
by forcing a test pattern at the output pins and capturing test results at
the input pins.
allows the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation.
and
allowing the
allows the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation, while tri-stating all
of the I/O pins.
allows the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation while holding I/O
pins to a state defined by the data in the boundary-scan register.
Used when configuring a Stratix III device via the JTAG port with a
USB Blaster™, ByteBlaster™ II, MasterBlaster™ or ByteBlasterMV™
download cable, or when using a Jam File, or JBC File via an
embedded processor.
though the physical pin is unaffected.
JTAG testing. Can be executed before, after, or during configurations.
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
TDO
pins, allowing the
IDCODE
IDCODE
USERCODE
register and places it between
nCONFIG
to be serially shifted out of
USERCODE
Description
Stratix III Device Handbook, Volume 1
register and places it between the
pin low to trigger reconfiguration even
to be serially shifted out of
HIGHZ
TDI
TDI
TDI
,
TDO
CLAMP
and
and
and
TDI
.
TDO
TDO
TDO
, and
and
pins, which
pins, which
pins, which
EXTEST
TDO
TDI
TDO
13–9
,
®
II
.
.